What’s New in Quartus II Software v14.1

Altera’s latest design software release, Quartus^® II software v14.1, now supports both Generation 10 devices – Arria^® 10 and MAX^® 10 – in a single download.

The support for Arria 10 and MAX 10 devices are summarized in Table 1.

Table 1. Quartus II Software v14.1 Support for Arria 10 and MAX 10 Devices

Productivity Advantage

Multiple Design Flows for DSP Hardened Floating-Point Blocks

You can harness the performance and productivity advantages of hardened floating-point blocks in Arria 10 devices. With a hardened floating-point adder and multiplier in every DSP block, Arria 10 devices deliver up to 1.5 tera floating point operations per second (TFLOPS) of performance while reducing your floating-point design resources by 80 percent compared with previous implementations. With Quartus II software v14.1, you can realize the benefits of the hardened floating-point implementation through multiple design flows that include a model-based, C-based, and RTL-based design flow:

• Model-based design flow with DSP Builder and MathWorks Simulink
  • DSP Builder enables automatic high-performance push-button HDL generation of DSP algorithms directly from the Simulink environment
  • The updated DSP builder libraries include enhanced Math.h functions and updated design examples that support DSP blocks with hardened floating-point operators
• C-based design flow with the Altera^® SDK for OpenCL^TM*
  • The Altera SDK for OpenCL allows users to abstract away the traditional hardware FPGA development flow for a much faster and higher level software development flow.
  • The compiler automatically optimizes the hardware implementation by taking advantage of the floating-point operators in the DSP blocks.
• RTL-based design flow with IP cores
  • You can develop floating-point algorithms by instantiating Altera’s floating-point megafunctions and MegaCore^® functions directly from your RTL code.
  • A wide range of mathematical functions support the hardened floating-point implementation (e.g. add, subtract, multiply, dot product, and accumulator).
  • The matrix multiplier megafunction and fast Fourier transform (FFT) MegaCore function also support the hardened floating-point implementation

Serial Link Planning Tool

The JNEye link analysis tool makes a significant leap with new channel analyzer capabilities that includes support for different transmission line models (e.g. stripline and single via). The JNEye link analysis tool also performs new causality and passivity checks, and reports several new measures of noise.

For more information, visit the JNEye web page.

Enhanced IP Integration

A new IP integration flow that is composed of a migration wizard and a centralized IP catalog simplifies the IP selection and migration to new Altera devices.

Design Space Explorer

Quartus II software v14.1 also offers an enhanced next-generation Design Space Explorer (DSE), a simple and easy-to-use design optimization tool that explores and reports Quartus II software options that are optimal for your design. DSE 2.0 enables faster convergence to the optimal Quartus II software settings with new exploration strategies and efficient farming of compiles to workload management software, namely LSF or Sun Grid.

Faster Simulation with the ModelSim-Altera Edition Software

The ModelSim^®-Altera Edition simulation software provided with Quartus II software v14.1 boosts Altera IP simulation runtime by 80 percent.

Performance Advantages

High-End FPGA Performance

Quartus II software v14.1 offers a performance advantage over the competition with Altera’s high-end FPGAs, delivering a 20 percent advantage in f_MAX over its nearest competitor.

System Integration Tool

Qsys, Altera’s system integration tool that uses a network on a chip (NoC) architecture, delivers a 20 percent performance advantage over the competing system integration tool. In Quartus II software v14.1, Qsys enables the creation of subsystems and the rearranging of components on-the-fly. Now, existing components can be pushed into subsystems, or pulled out. Qsys also offers a new clock and reset domain visualization tool to enable quick debug of this critical area of system designs.

Altera SDK for OpenCL

Altera continues its leadership in the industry with the Altera SDK for OpenCL, the only conformant OpenCL SDK for FPGAs in full production release. Combining Open Computing Language (OpenCL), an open standard parallel programming language, with the parallel performance capabilities of an FPGA provides a powerful solution for system acceleration. Using the Altera SDK for OpenCL, you can abstract away the traditional hardware FPGA development flow for a much faster and higher level software development flow.

In the v14.1 release, the Altera SDK for OpenCL continues its industry-leading performance-per-watt advantage through improvements to the QoR of the compiler, emulator, and rapid prototyping flow to support Altera’s Arria 10 FPGAs and SoCs. Through this release, even software programmers can achieve up to 1.5 TFLOPS of FPGA floating-point performance through Altera’s programmer-friendly OpenCL solution.

OpenCL^TM and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos.
* Product is based on a published Khronos Specification, and has passed the Khronos Conformance Testing Process. Current conformance status can be found at www.khronos.org/conformance.